High Speed serial interfaces span many standardisation efforts; these include the DigRF/M-PHY interface developed by the Mobile Industry Processor Interface (MIPI) Alliance, Universal Serial Bus (USB) interface, serial Rapid Input Output (sRIO) bus interface, Common Public Radio Interface (CPRI), Open Base Station Architecture Initiative (OBSAI) interfaces, etc. Key requirements for such high speed interfaces include high baud rates with minimal power consumption, low bit error rate and minimal Electromagnetic Interference (EMI). Many electronic products that include high-speed serial interfaces also contain wireless functionality. A mobile telephone device is one such example. Mitigating the effect of high-speed serial communication generated interference, as caused to the receiver or transmitter functionality, is paramount to the effective operation of the wireless functionality.
The MIPI developed M-PHY interface configured in DigRF mode is a high speed interface comprising requirements for EMI that are particularly sensitive, due to the fact that the interface is connecting the radio frequency integrated circuit (RFIC) transceiver device and the baseband processor integrated circuit (BBIC) within a communication device. The RFIC transceiver device in a mobile phone processes the low level signals received from the air-interface. In a DigRF M-PHY interface, there is a requirement for more than 1 Gbs on the downlink from the RFIC to the BBIC and greater than 832 Mbps on the uplink from the BBIC to the RFIC for some 3GPP LTE (3rd Generation Partnership Project Long Term Evolution) use case examples.
The proliferation of embedded clock schemes such as 8b10b coding in serial interfaces to facilitate clock data recovery also has an undesired consequence of shaping the resultant spectrum. The frequency lobes generated are maximally flat across the spectrum with nulls only at the baud frequency. Data streams without embedded clocks encoded tend to have more roll off at higher frequencies such that the RF spectrum exhibits a SING profile. Typically, the baud rate needed to meet the increased data throughput requirements would be such that data transmitted at these rates would result in a RF spectrum of the data signal that could interfere significantly with critical RF channel frequencies. Furthermore, as the baud rate is increased, the noise impact can become more significant.
One possible solution to this problem is to use more than one data path. In this manner, data may be transmitted at a lower data rate over a plurality of lanes, thus providing the required high data throughput whilst maintaining a low baud rate. However, increasing the number of data paths requires an increase in the number of data pins of the respective integrated circuits and semiconductor devices. As will be appreciated, increasing the number of pins results in an increase in the power consumption (due to the need to drive each pin) and complexity in terms of synchronising and time controlling the data paths. Furthermore, each additional path increases the composite noise by 3 dB. Accordingly, there is a trade-off between the number of data paths, with their inherent power and complexity costs and composite noise increases, and the interference caused by higher baud rates.